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ICS601-01 Low Phase Noise Clock Multiplier
Description
The ICS601-01 is a low cost, low phase noise, high performance clock synthesizer for any applications that require low phase noise and low jitter. It is ICS' lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using ICS' patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10-27 MHz crystal or clock input, and produces output clocks up to 156 MHz at 3.3 V.
Features
* Packaged in 16 pin SOIC or TSSOP * Uses fundamental 10 - 27 MHz crystal, or clock * Patented PLL with the lowest phase noise * Output clocks up to 156 MHz at 3.3 V * Low phase noise: -132 dBc/Hz at 10 kHz * Output Enable function tri states outputs * Low jitter - 18 ps one sigma * Full swing CMOS outputs with 25 mA drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * Industrial temperature version available * 3.3 V or 5 V operation
Block Diagram
VDD
Reference Divide
X1/ICLK
Phase Comparator
Charge Pump
Loop Filter
VCO
Output Buffer
CLK
Crystal Oscillator
X2
VCO Divide ROM Based Multipliers Output Buffer REFOUT
GND
S3 S2 S1 S0
OE
REFEN
1 Revision 090800 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 601-01 G
ICS601-01 Low Phase Noise Clock Multiplier
Pin Assignment
CLK REFEN VDD VDD VDD X2 S1 X1/ICLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND GND GND REFOUT OE S0 S3 S2 Multiplier Select Table
S3 S2 S1 S0 CLK (see note 2 on following page) 0 0 0 0 TEST 0 0 0 1 TEST 0 0 1 0 Input x1 0 0 1 1 Input x3 0 1 0 0 Input x4 0 1 0 1 Input x5 0 1 1 0 Input x6 0 1 1 1 Input x8 1 0 0 0 TEST 1 0 0 1 Crystal osc. pass through (no PLL) 1 0 1 0 Input x2 1 0 1 1 TEST 1 1 0 0 Input x8 1 1 0 1 Input x10 1 1 1 0 Input x12 1 1 1 1 Input x16 0=connect directly to ground 1=connect directly to VDD
ICS601-01
Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name CLK REFEN VDD VDD VDD X2 S1 X1/ICLK S2 S3 S0 OE REFOUT GND GND GND Type O I P P P XO I XI I I I I O P P P Description Clock output from VCO. Output frequency equals the input frequency times multiplier. Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low. Connect to +3.3V or +5V. Must match other VDDs. Connect to +3.3V or +5V. Must match other VDDs. Connect to +3.3V or +5V. Must match other VDDs. Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal. Multiplier select pin 1. Determines CLK output per table above. Internal pull-up. Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock Multiplier select pin 2. Determines CLK output per table above. Internal pull-up. Multiplier select pin 3. Determines CLK output per table above. Internal pull-up. Multiplier select pin 0. Determines CLK output per table above. Internal pull-up. Output Enable. Tri-states both output clocks when low. Internal pull-up. Buffered crystal oscillator clock output. Controlled by REFEN. Connect to ground. Connect to ground. Connect to ground.
Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; XI, XO = crystal connections. 2 Revision 090800 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 601-01 G
ICS601-01 Low Phase Noise Clock Multiplier
Achieving Low Phase Noise
Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that can be taken to achieve these levels of phase noise from the ICS601-01. Variations in VDD will increase the phase noise, so it is important to have a stable, low noise supply voltage at the device. Use decoupling capacitors of 0.1 F in parallel with 0.01 F. It is important to have these capacitors as close as possible to the ICS601-01 supply pins. Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this can reduce the phase noise by as much as 10 dBc/Hz.
0
-20
-40
Phase Noise (dBc/Hz)
-60
-80
-100
-120
-140 10.0E+0
100.0E+0
1.0E+3
10.0E+3
100.0E+3
1.0E+6
10.0E+6
Offset from Carrier (Hz)
Figure 1. Phase Noise of ICS601-01 at 125 MHz out, 25 MHz crystal input. VDD = 3.3 V, REFOUT disabled.
External Components/Crystal Selection
The ICS601-01 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01 F and 0.1 F should be connected between VDD and GND, as close to the part as possible. A series termination resistor of 33 may be used for each clock output. The crystal must be connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. In general, the value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL -5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used. For any given board layout, ICS can measure the board capacitance and recommend the exact capacitance value to use. 3 Revision 090800 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 601-01 G
ICS601-01 Low Phase Noise Clock Multiplier
Electrical Specifications
Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Ambient Operating Temperature, I version Soldering Temperature Storage temperature Operating Voltage, VDD Input High Voltage, VIH, X1/ICLK pin only Input Low Voltage, VIL, X1/ICLK pin only Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH, CMOS level Output High Voltage, VOH Output Low Voltage, VOL Operating Supply Current, IDD Short Circuit Current Input Capacitance Input Frequency Output Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Maximum Absolute Jitter, short term, 125 MHz Maximum Jitter, one sigma, 125 MHz (x5) Phase Noise, relative to carrier, 125 MHz (x5) Phase Noise, relative to carrier, 125 MHz (x5) Phase Noise, relative to carrier, 125 MHz (x5) Phase Noise, relative to carrier, 125 MHz (x5) Notes: Conditions Referenced to GND Referenced to GND Industrial temperature Max of 10 seconds Minimum Typical Maximum 7 VDD+0.5 70 85 260 150 5.5 (VDD/2)-1 2 0.8 IOH=-4mA IOH=-12mA IOL=12mA No Load, 125 MHz Each output OE, select pins VDD-0.4 2.4 22 60 5 0.4 30 Units V V C C C C V V V V V V V V mA mA pF MHz MHz ns ns % ps ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz
ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5 0 -40 -65 3.0 (VDD/2)+1
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Note 3 Note 3
40
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
10 at 3.3V or 5V 0.8 to 2.0V, no load 0.8 to 2.0V, no load At VDD/2 No load, REF off No load, REF off 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 27 156 1.5 1.5 55 75 25
45
-105 -120 -128 -121
50 50 18 -108 -123 -132 -125
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. The phase relationship between input and output can change at power up. For a fixed phase relationship, see the ICS570 or ICS670. 3. Switching occurs nominally at VDD/2.
4 Revision 090800 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 601-01 G
ICS601-01 Low Phase Noise Clock Multiplier
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC no. 95.) 16 pin narrow SOIC, TSSOP (in mm)
Symbol A A1 B C D E H e L SOIC Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 5.80 6.20 1.27 BSC 0.40 1.27 TSSOP Min Max 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.65 BSC 0.45 0.75
E
H
D A1 e B C L A
Ordering Information
Part/Order Number ICS601M-01 ICS601M-01T ICS601M-01I ICS601M-01IT ICS601G-01 ICS601G-01T Marking ICS601M-01 ICS601M-01 ICS601M-01I ICS601M-01I ICS601G-01 ICS601G-01 Shipping packaging tubes tape and reel tubes tape and reel tubes tape and reel Package Temperature 16 pin narrow SOIC 0 to 70 C 16 pin narrow SOIC 0 to 70 C 16 pin narrow SOIC -40 to 85 C 16 pin narrow SOIC -40 to 85 C 16 pin TSSOP 0 to 70 C 16 pin TSSOP 0 to 70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
5 Revision 090800 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 601-01 G

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